9. Hawk Interrupts and Traps

Contents

9.1. The Trap Vector
9.2. The Trap Registers
9.3. A Trap Service Example

9.1. The Trap Vector

RESTARTTRAP     = #00
BUSTRAP         = #10
INSTRTRAP       = #20
PRIVTRAP	= #30

The lowest memory addresses in a Hawk machine are known as the trap and interrupt vector area. Whenever the CPU detects an abnormal condition, either the result of an internal or an external condition, control is transferred to a location in the trap vector. The special conditions detected internally are:

Restart -- location #00

A restart trap indicates that the machine should start over. An external interrupt may indicate this condition; currently, none do.

Bus -- location #10

A bus trap occurs when the CPU attempts to fetch from nonexistant memory or when the CPU attempts to store in nonexistant or read-only memory. Usually, this indicates that the program currently running has gone awry, either by following an invalid pointer or by returning from a subroutine after corrupting its return address.

Instruction -- location #20

An instruction trap occurs when the CPU attempts to execute an undefined instruction. Usually, this occurs when the CPU attempts to execute data, for example, because a program in read-write memory corrupted itself or because subroutine after corrupting its return address and then tried to return.

Privilege -- location #30

A privileged instruction (CPUGET or CPUSET) was executed in user state.

9.2. The Trap Registers

  TPC - the trap program counter
  TMA - the trap memory address
  TSV - the trap save register

These registers are documented more fully in the section on processor control registers Each of these registers can be manipulated with the CPUGET and CPUSET instructions.

When an interrupt or trap occurs, the CPU stores the program counter in the trap program counter register; if the trap occurred because of a memory addressing fault, the memory address and a notice of the cause is stored in the trap memory address register, and the trap save register is needed by trap service software. In addition to setting TPC and TMA, traps and interrupts also copy the level field of the PSW into the old-level field, and set the level field to zero. This has the effect of making the trap service routine uninterruptable and privileged, and it turns off the memory management unit.

9.3. A Trap Service Example

The following code illustrates how a trap may be intercepted by software with the entire system state saved. Here, we assume that the trap vector itself is in ROM, that statically allocated RAM addresses are used for register save areas associated with each entry in the trap vector, and that there are no recursive trap service routines.

; code to handle illegal memory references
.       =       BUSTRAP
        CPUSET  R1,TSV          ; save R1
        LOAD    R1,busref	; get the save area pointer
        JUMP    trapcode	; join common code for all traps
	ALIGN	4
busref:	W	bussavearea

The above bit of code occupies exactly 16 bytes (with room for one halfword of additional code) and allows each trap to be handled using its own register save area. The common code shared by all trap service routines saves the registers in the save area as follows:

trapcode:	; enter with R1 pointing to save area
	STORE	R2,R1,svR2
	STORE	R3,R1,svR3
	CPUGET	R2,TSV
	CPUGET	R3,TPC
	STORE	R2,R1,svR1
	STORE	R3,R1,svPC
	CPUGET	R2,TMA
	CPUGET	R3,PSW
	STORE	R2,R1,svMA
	STORE	R3,R1,svPSW

        ; ... straightforward code to save other registers

	LOAD	R2,R1,myPSW
	LOAD	R3,R1,myCODE
	CPUSET	R2,PSW		; typically enables interrupts
	JSRS	R3,R3		; go serve the trap

        ; ... code to restore other registers

	LOAD	R3,R1,svPSW
	LOAD	R2,R1,svPC
	CPUSET	R3,PSW
	CPUSET	R2,TPC
	LOAD	R3,R1,svR3
	LOAD	R2,R1,svR2
	LOAD	R1,R1,svR1
	RTT			; return to user!

The above code is written using R2 and R3 as alternate temporaries in order to improve pipeilined execution. On a superscalar machine, it might be best to use R2 through R5 in order to allow even more parallelism. If speed is no issue, only one temporary register is needed in addition to the save area pointer. The number of instructions needed does not change, however.

The save area specific to each trap service routine, and pointed to by R1 in the above code, is assumed to be a record with field offsets declared something like the following:

; trap save area record structure
; (all fields are 1 word, so displacements are shown in words)

svPSW=  0 <<2	; save area for PSW
svR1 =  1 <<2	; save area for registers
svR2 =  2 <<2
svR3 =  3 <<2
svR4 =  4 <<2
svR5 =  5 <<2
svR6 =  6 <<2
svR7 =  7 <<2
svR8 =  8 <<2
svR9 =  9 <<2
svRA = 10 <<2
svRB = 11 <<2
svRC = 12 <<2
svRD = 13 <<2
svRE = 14 <<2
svRF = 15 <<2
svPC = 16 <<2	; save area for PC
svMA = 17 <<2	; save area for trap MA
myPSW= 18 <<2	; initial PSW to use for trap service
myCODE=19 <<2	; pointer to trap-specific routine entry

The trap and interrupt entry sequence runs with the level field of the PSW set to zero, preventing interrupts. Once the state of the interrupted code is saved, the PSW should be set with a level field that enables those interrupts that are allowed during the service of this trap or interrupt. This is specified in the myPSW field of the trap service record. of the unique trap service routine that handles that trap.

This approach to trap service is at the extreme RISC end of the spectrum! Many machines include complex trap entry hardware that automatically saves and restores blocks of registers.