Part of
the Hawk Manual
by
Douglas W. Jones
THE UNIVERSITY
OF IOWA
Department of Computer Science
1.1. Summary
1.2. Memory Resources
1.3. CPU Resources
1.3.1. General Purpose Registers
1.3.2. Program Counter
1.3.3. Processor Control Registers
1.3.3.1. Processor Status Word and Condition Codes
1.3.3.2. Trap Program Counter
1.3.3.3. Trap Memory Address
1.3.3.4. Trap Save Register
1.3.3.5. Cycle Counter Register
1.3.3.6. Memory Management Unit Data Register
1.3.4. Memory Management Unit
1.4. The Instruction Execution Cycle
1.5. Other Notational Conventions
The Hawk computer is a fictional machine that incorporates many features of modern RISC processors without slavish adherance to any particular real machine. The Hawk instruction set is based on a 32 bit word, typical for modern machines, and includes 15 general registers, a modest number by modern standards. All instructions are single-cycle, in the RISC tradition of machines like the IBM/Apple/Motorola Power architecture, the DEC Alpha architecture, the SGI MIPS architecture and the HP PA architecture. Unlike these machines, some of the Hawk instructions are variable-length, as with the older Intel 80x86/Pentium and Motorola 680x0 architectures.
With all computers, it is conventional to number the bits and other fields within in a word. The numbering of is entirely arbitrary; for the Hawk, we will arrange things as shown below:
_______________________________________________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| |31 24|23 16|15 8|7 0| | byte 3 | byte 2 | byte 1 | byte 0 | | halfword 1 | halfword 0 | | word |
This numbering conforms to the numbering used in DEC's 16, 32 and 64 bit computers; a numbering scheme that was later used by Intel. IBM mainframes and Motorola's microcomputers number bits and fields in the opposite order.
Note that the Hawk word is 32 bits, while the 16 bit quantity is called a halfword. This usage is exactly the same as has been used on IBM mainframes since 1965, but it differs from standard Intel, Motorola and DEC usage, all of which date back to the early 1970's when a 16 bit word was natural on minicomputers and microcomputers. As with the numbering of fields, the particular unit called a word or a byte is entirely arbitrary.
A Hawk memory address is a 32 bit quantity (one word) with the following layout:
_______________________________________________________________
|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
|31 12|11 2|1 0|
| page word in page |byte
word
The high 30 bits of the address specifies one word in memory, while the low two bits may be used to specify a byte in that word. Thus, the Hawk memory consists of up to 230 words or up to 232 bytes, which is 4 gigabytes. These figures are typical of computers designed since the 1970's, and as with typical computers built since the mid 1950's, it is unlikely that all memory addresses will refer to real memory!
Note that, for some purposes, the word field of the memory address may be broken into page and word-in-page fields. In this case, each page consists of 210 words, and the entire address space contains 220 pages.
In the following descritpion, the Hawk memory will be viewed as an array of words, with addresses ranging from 0 to 232-1, with groups of 4 consecutive addresses all referencing the same word in memory. Thus, addresses 0, 1, 2 and 3 all refer to the first word in memory, addresses 4, 5, 6 and 7 all refer to the second word, and so on up to addresses 232-4, 232-3, 232-2 and 232-1, which all refer to the final word in memory. To simplify discussion, memory addresses will frequently be described as viewed as records with a 30 bit word field and a 2 bit byte field.
The Hawk memory may also be viewed as an array of bytes, with addresses ranging from 0 to 232-1, so that address 0 refers to the first byte, which is stored in the first word, and address 1 refers to the second byte, which is also stored in the first word. This overlapped view of memory as either an array of bytes or of words dates back to the IBM System 360 family of mainframes, introduced in 1965, and this view is shared by all but the very smallest of modern computers.
The Hawk instruction set does not directly support non-aligned memory references. Thus, if bytes 3, 4, 5 and 6 are to be treated as one word, user software must compose this from byte 3, stored in one word, and bytes 4, 5 and 6, stored in the next consecutive word.
The Hawk Central Processing Unit contains 17 registers. 15 of these registers are general purpose registers, each of which holds one word and each of which may be used to hold variables during the execution of a program. In addition, one special register is reserved to hold the address of the next instruction to be fetched by the CPU. This is the program counter. Finally, there is a condition code register, used to record results of computations and to control the CPU response to various special conditions.
The Hawk has 15 general purpose registers, numbered 1 to 15; these may be viewed as an array of 15 words, and the CPU also allows references to general purpose register 0, but register 0 always contains the value 0 and attempts to store values in it are ignored. This usage is closely related to that on the IBM 360 family, dating back to 1965, and many other computers, including the highly influential DEC VAX share similar structures.
In assembly language programs, the names R1 to R15 should be used for the general purpose registers, and the name R0 may be used for the 16th register that holds the constant 0. In formal descriptions of the architecture, registers will be referenced as r[0] through r[15].
The CPU executes programs by fetching successive instructions from memory and executing them. The program counter is the register used to hold the address of the next instruction in memory that is awaiting execution. Instructions on the Hawk are composed of 16 bit half-words (as in the IBM 360), so the program counter may be viewed either as a 32 bit register where the least significant bit is always 0 or as a 31 bit register. In either case, 30 bits of the program counter specify which word contains the next instruction, and 1 bit specifies which half of that word should be used. In formal descriptions, the program counter will be referenced as pc, with fields pc.word (the top 30 bits) and pc.byte (the bottom 2 bits).
_______________________________________________________________
|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
|31 2|1 0|
word byte
The Hawk CPU includes 6 special registers:
All programmers must understand the least significant bits of the processor status word; these are the condition codes, used to report on the results of selected instructions. The remainder of these special registers only concern system programmers.
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|_|_|_|_|_|_|_|_|///////////////|_|_|_|_|_|_|_|_|///////|_|_|_|_|
|31 28|27 24|23 16|15 8|7 4|3 0|
| | | | | |N Z V C|
level old bcd condition
level carry codes
From the programmer's perspective, the 4 condition code bits are the most important bits in the processor status word. These are used to store the results of selected instructions so that the results can be tested or used to form boolean values. Condition codes were first introduced on the IBM System 360 mainframes in 1965, and the particular set used here was first introduced on the DEC PDP-11 in 1970. Not all instructions set the condition codes, but most that set them use the following meanings:
setcc(x>>s) returns z = x>>s and set N if z < 0 set Z if z = 0 reset V set C if any one bits shifted out of low end of x the bcd-carry field becomes undefined, except that the high bit of bcd-carry is the C bit. setccv(x+(y<<s)) returns z=x+(y<<s) (truncated to 32 bits) and set N if z < 0 set Z if z = 0 set V if z has the wrong 2's complement sign with respect to the signs of x and y set C if any one bits were discarded in truncating the result to 32 bits. set the bcd-carry field to the carry out from each 4-bit nibble of the sum; note that in this case, C and the high bit of the bcd-carry field will be equal! setccz(x) returns x and set N if x < 0 set Z if x = 0 reset V set C if any 8-bit byte of x is zero the bcd-carry field becomes undefined, except that the high bit of bcd-carry is the C bit. setccx(f(x,y)) returns z = f(x,y) and set N if z < 0 set Z if z = 0 set V if the sign of y differs from any bits discarded from the left end of x. set C if any one bits were discarded from the left end of x. the bcd-carry field becomes undefined, except that the high bit of bcd-carry is the C bit.
Where the bcd-carry field is specified as becoming undefined, future versions of the architecture may add functionality where none is currently specified.
The function cond(x) is used in formal descriptions to describe the 16 condition code tests provided for by the Hawk architecture. These are:
x cond(x) x cond(x)
0000 false 1000 true
0001 ~N 1001 N
0010 ~Z 1010 Z
0011 ~V 1011 V
0100 ~C 1100 C
0101 ~N xor V 1101 ~(~N xor V)
0110 ~(N or Z) xor V 1110 ~(~(N or Z) xor V)
0111 C and ~Z 1111 ~(C and ~Z)
In this table, the unary operator ~ means logical not, and xor means exclusive or.
The 8-bit bcd-carry field is used to support binary coded decimal and excess-three decimal arithmetic; each bit of this field contains the carry bit out of the corresponding BCD or excess three digit (4 bit field) of the most recent 32 bit sum. In formal instruction definitions, the notation spread-bcd-carry will be used to refer to the contents of this field, spread out to make a 32-bit value by inserting 3 zero bits after each of the 8 bits in this field.
The level field of the PSW indicates the current level at which the CPU is operating, with regard to interrupts and traps. Level 0000 disables all. Level 1111 enables all interrupts and prohibits execution of privileged instructions. Interrupts and traps save the current level in the old-level field and set the level to 0000. The high bit of the level field controls the memory management unit, and in some machine configurations, it may control other peripherals as well.
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|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
|31 2|1 0|
word byte
When an instruction causes a trap, for example, when an instruction references an illegal address or when the opcode field is invalid, the program counter is saved in the Trap Program Counter register. The value saved is the address of the offending instruction.
When an interrupt is requested, the trap program counter is used to save the address of the instruction to be executed on return from interrupt.
_______________________________________________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| |31 12|11 2|1 0| | page word in page | | | address |cause
When a trap is caused by an illegal memory reference, the offending memory address is saved in the high 30 bits of the Trap Memory Address register. If the memory management unit is turned off (psw.priority < 8), the least significant bits of the TMA register will always be zero. If the memory management unit is turned on (psw.priority > 7), the least significant two bits report the nature of the trap with reference to the R, W, X and V bits in the memory management unit.
00 -- reference page was invalid (V = 0) 01 -- fetch attempted from non-code page (X = 0) 10 -- operand store attempted to non-writable page (W = 0) 11 -- operand load attempted from non-readable page (R = 0)
_______________________________________________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| |31 0|
This is a simple 32 bit register, with no special hardware function. It is needed as a temporary register in order to save and restore registers during trap service entry and exit.
_______________________________________________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| |31 0|
This is a simple 32 bit register that is incremented whenever the CPU performs any operation on memory (fetch, load or store). Sampling the cycle count is a useful way to measure the run-time cost or performance of a program.
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|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|///////////|_|_|_|_|_|_|
|31 12|11 6|5|4 0|
physical page unused G C R W X V
number
The memory management unit data register is used to load or store information about pages in the virtual address space.
A read from the MMU Data Register gives the information associated with the page currently selected by the Trap Memory Address register, while a write to the MMU Interface Register causes the MMU to associate the given information with the page selected by the Trap Memory Address register.
The least significant bits of the MMU Data Register are defined as follows:
The Hawk CPU contains a memory management unit. This unit is fairly simple compared to those of many modern computers, but like the memory management units of other computers, it translates the virtual addresses used by user programs into physical memory addresses. As on other machines, most programmers can ignore the presence of the memory management unit, but system programmers must deal with it.
The Hawk memory management unit is turned off whenever the high bit of the priority field of the processor status word is zero; therefore, the occurance of an interrupt or trap always turns off the memory management unit.
The Hawk memory management unit consists of an array of mapping registers, each of which is seen as two 32 bit fields by the software. The first of these fields corresponds to the Trap Memory Address register, while the second field corresponds to the MMU Data Register:
_______________________________________ _______________________
|_______________________________________|///////////////////////|
|31 12|11 0|
virtual page unused
number
_______________________________________ _______________________
|_______________________________________|/////////////|_|_|_|_|_|
|31 12|11 5|4 0|
physical page unused C R W X V
number
In operation, each time the CPU issues a virtual address, the memory management unit searches for a mapping register that contains the corresponding virtual page number field, and then substitutes the physical page number for the virtual page number in order to construct a physical address.
If the CPU attempts to reference an address that involves an invalid memory management unit entry, or if the CPU attempts to read, write or execute using an address where those operations are forbidden because the R, W or X bits are zero, the memory management unit will force a trap and store the address that caused the trap in the TMA register along with an indication of the cause.
The number of mapping registers in the memory management unit may vary from machine to machine, but the software need not know how many registers there are nor how they are searched. Technically, the search may be either fully associative or set-associative. When a new association is stored in the memory management unit, the particular mapping register to be used is determined by an internal MMU replacement policy that may vary from one machine to another.
When needed, the contents of all mapping registers may be invalidated by using the G bit in the MMU Data Register with the V bit set to zero.
The instruction execution cycle of any computer can be described by a computer program that performs the same computations as that computer. The definitive descriptions of most new architectures developed since 1970 have been given in a programming-language style of notation.
From this perspective, the Hawk architecture looks like most others. At the top level, the instruction execution cycle is described as follows:
repeat
if pc.byte = 0
ir = Memory[ pc.word ](bits 15 to 0)
else pc.byte = 2
ir = Memory[ pc.word ](bits 31 to 16)
pc = pc + 2
decode ir
execute ir
forever
This instruction execution cycle is essentially that proposed by Berks, Goldstein and Von Neumann back in 1946, even to the details of packing two instructions into each machine word! The original Von Neumann architecture, as it is generally called, was far simpler than the Hawk architecture, with only one accumulator instead of an array of general purpose registers, but the basic elements of machine architecture outlined by Berks, Goldstein and Von Neumann over 50 years ago have not changed greatly.
The instruction register, ir formally, has a number of fields; these are defined here; many fields have multiple names, and many fields overlap.
_______________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| |15 12|11 8|7 4|3 0| | op | dst | s1 | s2 | | | | op1 | x | | | | | src | | | | | op2 | | | | const |
The particular fields used depend on the op field, and sometimes on the op2 field. Details of the fields used by each group of instrucions are given with the definitions of those instructions. In all cases, the op field(s) are used to determine which instruction is used. The fields are summarized here:
In descriptions of the effects of instructions, the following notations will commonly be used: