3. Hawk Memory Reference Instructions

Part of the Hawk Manual
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Contents

  • 3.1. Format
  • 3.2. Load Address
  • 3.3. Load
  • 3.4. Branch and Call
  • 3.5. Store

     

    3.1. Format

    Memory Reference Format 

     _______________________________
|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
|15   12|11    8|7     4|3     0|
|1 1 1 1|  dst  |0      |   x   |
 _______________________________
|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
|15                            0|
|             disp              |
    The basic memory reference instructions are 32 bits long, with the extra 16 bits coming from the next successive 16 bit halfword in memory following the instruction itself.

    The effective memory address referenced by such an instruction is formed by sign-extending the 16 bit displacement to 32 bits and adding it to the specified index register: 

         ea = r[x] + sxt(disp)
    In this special case, when x = 0, r[x] refers to the program counter. As a result, indexed addressing using r[0] is relative to the address of the immediately following instruction. This allows easy reference to any location in the current program text.

    All of these instructions share the same assembly language formats: 

    	op	Rsrc,Rx,disp
	op	Rsrc,label
    The first format above is used for indexed addressing, where Rx is one of R1 through R15. The second form is used for PC relative addressing, where Rx is implicitly R0, and the assembler automatically computes disp as the difference between the current location and the addressed label. Thus, the following two lines of assembly code are exactly equivalent: 
    	LOAD	R5,R0,label-(.+2)
	LOAD	R5,label
    Both generate the exact same machine code to load R5 with the contents of the location with the given label

     

    3.2. Load Address 

     1 1 1 1         0 1 1 1          LEA    r[dst] =          ea 
 1 1 1 1         0 1 1 0          LEACC  r[dst] = setccv(  ea )
    The effective address, ea, is loaded into the destination register, r[dst]. In the case of the LEACC instruction, the N, Z, V and C condition codes are set to indicate the result of the addition used to compute the effective address. If some word of memory is to be repeatedly loaded and stored, it is more efficient to load the address of that word into a register once and then use short memory reference format instructions for the repeated references to that word. 
     1 1 1 1         0 1 1 0          ADDI   r[dst] = setccv(  ea )
 1 1 1 1 0 0 0 0 0 1 1 0          CMPI            setccv(  ea )
    ADDI is provided as an alternative mnemonic for the LEACC because the instruction is also useful for adding an immediate constant to a register. Thus, the following instructions should produce identical machine code: 
    	LEACC	R1,R1,const
	ADDI	R1,R1,const
	ADDI	R1,const
    Note that assemblers for the Hawk machine will support both one-register and two-register forms of the ADDI instruction; the two-register form allows the sum to be computed from one register to another, while the one-register form is a convenient abbreviation for adding a constant to a register and is not assembled as a PC-relative LEACC instruction!

    Recall that if dst is zero, the loaded value is discarded. In the case of the LEACC instruction, this is useful because it allows the effective address to be tested for zero or a negative sign. In effect, this allows the index register x to be compared for equality to 16 bit displacement. Hawk assemblers should provide the mnemonic CMPI for this operation; assembly of the CMPI instruction should negate the displacement so that the resulting condition codes are easily interpreted. The following instructions should produce identical machine code to compare R1 with the constant 5: 

    	LEACC	R0,R1,-5
	CMPI	R1,5

    3.3. Load 

     1 1 1 1         0 1 0 1          LOAD   r[dst] =        m[ea]
 1 1 1 1         0 1 0 0          LOADCC r[dst] = setccz(m[ea])
    The contents of the designated word of memory, m[ea], are loaded into the destination register, r[dst]. In the case of the LOADCC instruction, the N and Z condition codes are set to indicate whether the indicated word is negative or zero, the V condition code is cleared, and the C condition code is set if any byte in the loaded value is zero. This feature allows for fast string operatons working with 4 bytes at a time. 
     1 1 1 1 0 0 0 0 0 1 0 0          TEST   r[dst] = setccz(m[ea])
    Recall that if dst is zero, the loaded value is discarded. In the case of the LOADCC instruction, this is useful because it allows the referenced word of memory to be tested for equality to zero or negative sign. Hawk assemblers should provide the mnemonic TEST for this operation, so that the following instructions are equivalent: 
    	LOADCC	R0,R0,label-(.+2)
	LOADCC	R0,label
	TEST	R0,label-(.+2)
	TEST	label
    All 4 instructions listed above should generate exactly the same machine code, producing a LOADCC instruction that uses the program counter as an index register to address the memory location with the given label, and then discards the result after setting the condition codes appropriately.

    The Hawk architecture does not allow direct loading or storing of bytes or halfwords. See the EXTB and EXTH instructions for efficient support of byte and halfword addressing.

     

    3.4. Branch and Call 

     1 1 1 1         0 0 1 1          JSR    r[dst] = pc; pc = ea
    The JSR (jump to subroutine) instruction stores the old value of the program counter, pc, in the destination register as a return address, and then sets the program counter to the effective address. The condition codes are not changed. 
     1 1 1 1 0 0 0 0 0 0 1 1          JUMP   pc = ea
    Recall that if dst is zero, the value is discarded. In the case of the JSR instruction, this is useful because it allows for a simple jump to the effective address.

    Assembly of the following instructions should produce exactly the same machine instructions: 

    	JUMP	label
	JUMP	R0,label-(.+2)
	JSR	R0,label
	JSR	R0,R0,label-(.+2)
    All 4 lines generate a JSR instruction that discards the return address and uses PC-relative addressing to transfer control to the indicated label.

     

    3.5. Store 

     1 1 1 1         0 0 1 0          STORE  m[ea] = r[dst]
    The contents of the designated register, r[dst] are stored into the indicated word of memory m[ea]. The condition codes are not changed. Note that the mnemonic dst (for destination register) is a misnomer here!

    Note that PC-relative STORE instructions should never be used when code is executed from read-only memory or from a read-only segment of the address space. Since one or the other of these will usually be the case, the PC-relative form of STORE should rarely find use!

    The Hawk architecture does not allow direct loading or storing of bytes or halfwords. See the STUFFB and STUFFH instructions for efficient support of byte and halfword addressing.