Part of
the Hawk Manual
by
Douglas W. Jones
THE UNIVERSITY
OF IOWA
Department of Computer Science
8.1. Format
8.2. Branch
8.3. Conditional Branch
_______________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| |15 12|11 8|7 4|3 0| |0 0 0 0| cond | disp |
The Branch format instructions are 16 bits each, incorporating a 4-bit branch condition and an 8 bit 2's complement branch displacement.
For all of these instructions, the effective address is formed by adding twice the displacement to the address of the immediately following instruction. This allows conditional branches to be taken to any instruction halfword within a 256 halfword range, with a displacement of zero referring to the immediately following instruction, positive displacements referring to later instructions, and negative displacements referring to earlier instructions.
Assemblers for the Hawk should automatically compute the appropriate displacement when given the symbolic label of the destination. Thus, if L is the label on some location in the code the notation
BR L
should cause, in effect, the assignment of the value of L to the program counter.
Note that branch instructions with a displacement of -1 create infinite loops; as such, Hawk hardware should detect and trap this combination! Also note that cond=1000 is unassigned and reserved for future applications.
0 0 0 0 0 0 0 0 BR branch always
Unconditional branch to the indicated destination. BR can be used wherever a program-counter-relative JUMP instruction is used, so long as the destination is one of the 256 reachable destinations for a branch instruction.
There are occasional contexts where an instruction that does absolutely nothing is required. All conditional branches do nothing if the displacement is zero, so any one of them could be used for this purpose, but BR with a displacement of zero is the preferred no-op for the Hawk machine.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP no operation
Thus, the following two assembly language instructions should generate exactly the same results:
NOP BR .+2
The fact that NOP is coded 000016 is a particularly convenient for ROM-based systems because, depending on how the ROM is coded, it either allows patching an existing ROM by overwriting arbitrary code with zeros, or it allows use of blocks of zeros as patch areas where code can be added later.
0 0 0 0 0 0 0 1 BNS branch if N set 0 0 0 0 0 0 1 0 BZS branch if Z set 0 0 0 0 0 0 1 1 BVS branch if V set 0 0 0 0 0 1 0 0 BCS branch if C set 0 0 0 0 0 1 0 1 BLT branch if less than 0 0 0 0 0 1 1 0 BLE branch if less than or equal 0 0 0 0 0 1 1 1 BLEU branch if less than or equal (unsigned) 0 0 0 0 1 0 0 1 BNR branch if N reset 0 0 0 0 1 0 1 0 BZR branch if Z reset 0 0 0 0 1 0 1 1 BVR branch if V reset 0 0 0 0 1 1 0 0 BCR branch if C reset 0 0 0 0 1 1 0 1 BGE branch if greater than or equal 0 0 0 0 1 1 1 0 BGT branch if greater than 0 0 0 0 1 1 1 1 BGTU branch if greater than (unsigned)
The conditional branch group of instructions allows 14 combinations of condition code settings to be tested. Both the format of this instruction and the use made of the condition codes date back to 1970, when they were used for the DEC PDP-11. Both the Intel 80x86/Pentium family and the Motorola 680x0 family have very similar branch instructions.
Hawk assemblers should define the following synonyms for conditional branch instructions:
0 0 0 0 0 0 1 0 BEQ branch if equal 0 0 0 0 0 1 0 0 BGEU branch if greater or equal (unsigned) 0 0 0 0 1 0 1 0 BNE branch if not equal 0 0 0 0 1 1 0 0 BLTU branch if less than (unsigned)
When there is a need to load a boolean into a register from the condition codes, a sequence of instrucitons such as the following can be used:
LIS R,TRUE BGT .+4 LIS R,FALSE
This sequence will load either TRUE or FALSE depending on the condition tested by the branch instruction. In this example, it will load R with TRUE if the GT condition was true (if the first operand was greater than the second in the immediately preceeding compare instruction of two signed operands), and FALSE otherwise.