Abstract

The past 25 years have been a very exciting time for computer architecture. A lot of this excitement was due to new opportunities made available by semiconductor technology: once basic uniprocessor functionality could be implemented on a chip, additional transistor resources could be used for innovative uniprocessor microarchitectures. The microarchitecture of uniprocessors was totally redefined by this wave of innovation. The net result is that the microarchitecture of a high-performance uniprocessor today barely resembles that of one from 20 years ago. And the rest of the computing community enjoyed continuous increases in performance in a completely transparent manner.

Today we are at the cusp of another inflection point in computer architecture. Technology allows for multiple processing cores to be put on a single chip; the resulting chip resembles a traditional small-scale multiprocessor. Going further, we expect a revolution in the architecture and microarchitecture of multicore chips (also know as chip multiprocessors (CMPs)), as technology advances provide us with more transistors with which to innovate. This revolution will encompass almost every aspect of multiprocessing, including new models for parallelization, new processor microarchitectures that trade off instruction-level parallelism for thread-level parallelism, new ways of allowing reliable operation from unreliable hardware components, and innovative ways of using storage components to architect memory hierarchies, among others. Unlike the past, however, software will not be able to reap the benefits of hardware innovation transparently. Applications and software will have to be more proactive in availing of the hardware capabilities, and certain types of applications may be better enabled than others.

This talk will present some initial results towards components of the overall revolution: innovations in the microarchitecture of multicore processors and memory hierarchies, and their likely impact on software and applications.